This invention relates to Ultra Thin (UT) Metal Oxide FET (MOSFET) devices. While the embodiment comprises a MOSFET device, as indicated by the title, the present invention can be embodied in Metal Insulator FET (MISFET) devices which employ gate dielectrics other than oxides. The term Ultra Thin (UT), as employed herein refers to Ultra Thin Channel (UTC) regions in SEMiconductor-On-Insulator (SEMOI) FET devices with the source and drain regions formed in thicker SEMOI or Silicon-On-Insulator (SOI) regions of a semiconductor substrate aside from the UTC regions. As employed herein the term SEMiconductor-On-Insulator (SEMOI) is a generic term which refers generally to structures of a semiconductor layer formed on an insulator such SOI, Silicon-Germanium-On-Insulator (SGOI), and Germanium-On-Insulator (GOI) structures. In SEMOI structures, in addition to SOI (silicon) and GOI (germanium) the semiconductor layer on top of the BOX layer may comprise other semiconductor materials such as silicon carbide, III-V compound semiconductors, and II-VI compound semiconductors.
There is a problem of fringing with a uniformly thick BOX layer extending under the channel. with a uniformly thin BOX layer, there will be fringing that will go through the BOX layer down into the substrate below the BOX layer, but when the BOX is thick, fringing goes over into the channel which is explained in an article by as stated at page 2096 Trivedi et al entitled “Scaling Fully Depleted SOI CMOS” IEEE Transactions on Electron Devices, VOL. 50, NO. 10, (October 2003), pp. 2095-2103. In addition thin BOX is undesirable in SOI CMOS devices because of electric field fringing in the BOX as described by V. P. Trivedi, et al entitled “Nanoscale FD/SOI CMOS: Thick or Thin BOX?” IEEE Electron Device Letters, Vol. 26, No. 1, (January 2005) pp. 26-28. Another problem with thin uniform BOX structures in CMOS devices is that the CMOS speed is reduced as stated by Trivedi in the above cited article. Still another problem is encountered, particularly with semiconductor devices with Raised Source/Drain (RSD) and Ultra-Thin Channel (UTC) semiconductor-on-insulator devices, which is the requirement for low raised source-drain for resistance forces the stressed liners to be located farther away from the channel than would be desired by the designer. For example a UTC SOI device with an RSD of 30 nm (including silicide) encounters a significant stress loss in the channel. The loss of performance due to the inefficient transfer of stress to the channel is compounded by the competing need to use sidewall insulating spacers which are as thick as possible, to minimize gate to source-drain capacitance. The present invention addresses these problems caused by loss of stress transferred to the channel of UTC SOI MOSFET devices. There is another problem which is that dislocations in a silicon substrate are caused by oxygen ion implanted into that silicon substrate. Referring to Nakai et al. U.S. Pat. No. 5,891,265 entitled “SOI Substrate Having Monocrystal Silicon Layer on Insulating Film”, the Abstract states as follows: “Oxygen ion is implanted into a silicon substrate to remain a silicon layer on a surface of the silicon substrate. In this state, a silicon oxide layer is formed under the silicon layer. Silicon oxide particles are formed and remained in the residual silicon layer. While maintaining this state, the silicon substrate is heated to a predetermined temperature not less than 1300° C. Alternatively, the silicon substrate is heated at a high temperature-rise rate to 900-1100° C., and thereafter is heated at a low temperature-rise rate to the temperature not less than 1300° C. The silicon substrate is held at the predetermined temperature not less than 1300° C. for a predetermined time, whereby crystallinity of the residual silicon layer is restored. A pinning effect of the silicon oxide particles prevents the rise of dislocation to the surface of the SOI layer, and also suppresses a rate per a unit time at which interstitial silicon generates during the heating to the high temperature region. Therefore, a dislocation density of the SOI layer can be reduced.” At Col 4, lines 6-18 Nakai states as follows: “In the manufacturing method according to the aspect of the invention, the silicon substrate is heated while remaining the silicon oxide particles in the silicon surface layer. Therefore, the silicon oxide particles formed and remaining in the silicon surface layer prevent dislocation from rising to and extending in a surface of the silicon surface layer by their pinning effect. This can prevent the dislocation from rising to the surface of the SOI layer (monocrystal silicon layer). Owing to the pinning effect described above, the existence of the silicon oxide particles prevents multiplication of the dislocation and stabilizes the same. Thereby, the dislocation density of the SOI layer can be remarkably reduced.”
Hsu et al. U.S. Published Patent Application 2005/0112811 for “Ultra-Thin SOI MOSFET Method and Structure” describes a raised source-drain UTSOI channel MOSFET. The embodiment of Hsu et al. is an example of the above described problem that it has high gate to source-drain capacitance and poor stress transfer to the channel. The lower surface of the UTSOI under channel is coplanar with the lower surface of the source-drain regions, as there is only a single BOX layer of uniform thickness. The source-drain regions are thicker than the channel, but are elevated. However, we have found that it would be preferred that they be recessed rather than elevated.
Wu U.S. Pat. No. 6,060,749 entitled “Ultra-Short Channel Elevated S/D MOSFETS formed on an Ultra-Thin SOI Substrate” and Wu, U.S. Pat. No. 5,956,580 entitled “Method to Form Ultra-Short Channel Elevated S/D MOSFETS on an Ultra-Thin SOI Substrate” describe a UTSOI MOSFET with thicker source-drain regions, but the thicker source-drain regions are elevated above the surface of the channel. To avoid high gate to source-drain capacitance very thick sidewall spacers are used, which results in very poor stress transfer if an overlying stress liner is used.
Choe U.S. Published Patent Application 2005/0067294 entitled “SOI by Oxidation of Porous Silicon” teaches methods of forming an SOI substrate using the porous silicon techniques including ion implantation of a p-type dopant, anodization, and oxidation as is well known in the art. The dopant is selected from the group consisting of p-type dopants such as Ga, Al, B and BF2, with B and BF2 being preferred. The resultant structure contains a blanket buried insulator, and another patterned layer of BOX.
Chen et al U.S. Pat. No. 6,429,091 entitled “Patterned Buried Insulator” a patterned buried insulator layers are formed below the future location of the source and drain regions by forming a mask over the body area and implanting a dose of n or p type ions to form buried doped layers. The dopant is implanted to make the silicon easier to etch. Then STI apertures intersecting the buried doped layers are formed by etching. The material which had formed in buried regions, when they were implanted, is then removed by etching through the STI apertures. A light oxidation is followed by a conformal oxide deposition into the STI apertures and also into the buried etched regions, thereby forming BOX regions alongside the STI apertures. Chen et al. does not teach the use of porous silicon to form BOX regions. Furthermore, Chen does not form the UTSOI region under the gate. The semiconductor under the gate is bulk and therefore suffers from the short channel scaling problems that our UTSOI structure solves. Chen does provide source-drain regions which are insulated from the substrate for reduced junction capacitance.